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Quiz #1

More about recitation quizes
Notes about file formats, comments, style, etc
The C Preprocessor
Makefile  and make

 Preparation  : Read the textbook and understand the lecture notes (www.cs.unm).
 

    You are not required to use any SPECIFIC set of rules for indenting, white space, comment headers, etc, BUT

    You MUST indent your code to reflect its actual block structure!   The specifics are up to you as long as you are consistent!  (emacs will do indenting for youautomatically!  Just type <TAB>!)
 

The C preprocessor provides four separate facilities that you can use as you see fit:

• Inclusion of header files. These are files of declarations that can be substituted into your program.

Including a header file produces the same results in C compilation as copying the header file into each source file that needs it. But such copying would be time-consuming and error-prone. With a header file, the related declarations appear in only one place. If they need to be changed, they can be changed in one place, and programs that include the header file will automatically use the new version when next recompiled.
 
• Macro expansion. You can define macros, which are abbreviations for arbitrary fragments of C code, and then the C preprocessor will replace the macros with their definitions throughout the program.

• Conditional compilation. Using special preprocessor commands, you can include or exclude parts of the program according to various conditions.

• Line control. If you use a program to combine or rearrange source files into an intermediate file which is then compiled, you can use line control to inform the compiler of where each source line originally came from.

        Makefile
            -Blank lines are ignored
            -Comments start with a #. A pound can be put anywhere in the makefile and the comment extends from the #to the end of the current line.

          -target: prerequesites (dependency)
            The target is a file(?) that will be updated if the prerequesites have been updated since the last make. In the case of a c++ program, the targets are object files and the executable file. The prerequisites are source and header files needed to build the target.
             -commands
               -grouped below the dependency line
               -a command line must begin with a tab !!

         Explanation:

            target: depend1 depend2
            <tab> command3

            depend1: source1
            <tab> command1

            depend2: source2
            <tab> command2
 

Example  from Assignment 1:

       ---Cut Here----

# Makefile for CS251 Program 1
# WARNING! WARNING! WARNING!
# DO >>NOT<< COPY THIS FILE from your browser window USING CUT-AND-PASTE!
#   IF YOU DO, THIS FILE WILL NOT WORK!
# See http://www.cs.unm.edu/~ackley/cs251/projects/makefile-warnings.txt
#   for more information!

# Compile-time flags
CFLAGS=-g -Wall -pedantic -c

# Command for compilation
CPP=g++

# Command for linking
LINK=g++

# Our application name
APP=blocks

# Our object files
OFILES=Board.o Block.o Main.o

# Default target
all:    $(APP)

# Linking the main app
$(APP): $(ALLDEP) $(OFILES)
        $(LINK) $(OFILES) -o $(APP)

# Compiling the source files
%.o:    %.C %.h $(ALLDEP)
        $(CPP) -c $(CFLAGS) $*.C -o $@

# Alternate target: cleaning
clean:
        rm -f *.o core *~

#######
# Other dependencies

Main.o: Board.h

Board.o: Block.h

       ---Cut Here----